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TDA7439
Three-band digitally-controlled audio processor
Features
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Input multiplexer - four stereo inputs - selectable input gain for optimal adaptation to different sources Single stereo output Treble, mid-range and bass control in 2-dB steps Volume control in 1-dB steps Two speaker attenuators: - two independent speaker controls in 1-dB steps for balance facility - independent mute function All functions are programmable via serial bus.
SDIP30
! ! ! !
high-quality audio applications in car-radio and Hi-Fi systems. Selectable input gain is provided. All the functions are controlled by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. The TDA7439 employs BIPOLAR/CMOS technology to provide low distortion, low noise and DC stepping.
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Description
The TDA7439 is a volume, tone (bass, mid-range and treble) and balance (left/right) processor for Table 1. Device summary
Order code TDA7439 SDIP30
Package Tube
Packaging
March 2008
Rev 11
1/23
www.st.com 23
Contents
TDA7439
Contents
1 2 3 Block diagram and pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 3.1.2 Bass, mid-range stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Treble stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 3.3
Pin CREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 4.2 4.3 4.4 4.5 4.6 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
I2C bus transmission examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 5.2 No address incrementing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address incrementing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
I2C bus addresses and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 6.2 6.3 Chip address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Sub-address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 8 9
Chip input/output circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23
TDA7439
Block diagram and pin out
1
Block diagram and pin out
Figure 1. Block diagram
MUXOUTL L-IN1 11 100K 12 100K 13 100K 14 100K 0/30dB 2dB STEP 100K 9 100K 8 VREF 100K 7 100K INPUT MULTIPLEXER + GAIN 17 MUXOUTR INR 18 28 TREBLE(R) RM 19 20 21 RB 22 2
D95AU342B
INL 16
TREBLE(L) 27
MIN(L) MOUT(L) BIN(L) 26 RM 25 23 RB
BOUT(L) 24
15
L-IN2
L-IN3
G
VOLUME
TREBLE
MIDDLE
BASS
SPKR ATT LEFT
6
LOUT
L-IN4
30 I CBUS DECODER + LATCHES
2
R-IN1
10
1 29
SCL SDA DIG_GND
R-IN2
G
VOLUME
TREBLE
MIDDLE
BASS
SPKR ATT RIGHT
5
ROUT
R-IN3
3 SUPPLY 4
R-IN4
VS AGND
MIN(R) MOUT(R) BIN(R)
BOUT(R) CREF
Figure 2.
Pin connections
SDA CREF VS AGND ROUT LOUT R-IN4 R-IN3 R-IN2 R-IN1 L-IN1 L-IN2 L-IN3 L-IN4 MUXOUTL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D95AU340A
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCL DIG_GND TREBLE(R) TREBLE(L) MIN(L) MOUT(L) BOUT(L) BIN(L) BOUT(R) BIN(R) MOUT(R) MIN(R) INR MUXOUTR INL
3/23
Electrical specifications
TDA7439
2
Electrical specifications
Table 2.
Symbol VS Tamb Tstg
Absolute maximum ratings
Parameter Operating supply voltage Operating ambient temperature Storage temperature range Value 10.5 0 to 70 -55 to 150 Unit V C C
Table 3.
Symbol Rth j-pin
Thermal data
Parameter Thermal resistance junction-pins Value 85 Unit C/W
Table 4.
Symbol VS VCL THD S/N SC
Quick reference data
Parameter Supply voltage Max. input signal handling Total harmonic distortion V = 1 V RMS, f = 1 kHz Signal to noise ratio Vout = 1 V RMS (mode = OFF) Channel separation f = 1 kHz Input gain (in 2-dB steps) Volume control (in 1-dB steps) Treble control (in 2-dB steps) Middle control (in 2-dB steps) Bass control (in 2-dB steps) Balance control (in 1-dB steps) Mute attenuation 0 -47 -14 -14 -14 -79 100 Min 6 2 0.01 106 90 30 0 +14 +14 +14 0 0.1 Typ 9 Max 10.2 Unit V V RMS % dB dB dB dB dB dB dB dB dB
Table 5. shows the electrical characteristics. Refer to the test circuit in Figure 3, Tamb = 25 C, VS = 9 V, RL= 10 k, generator resistance Rg = 600 , all controls flat (G = 0 dB), unless otherwise specified. Table 5.
Symbol Supply VS IS SVR Supply voltage Supply current Ripple rejection 6 4 60 9 7 90 10.2 10 V mA dB
Electrical characteristics
Parameter Test condition Min Typ Max Unit
4/23
TDA7439 Table 5.
Symbol Input stage RIN VCL Input resistance Clipping level THD = 0.3% The selected input is grounded through a 2.2 F capacitor
Electrical specifications Electrical characteristics (continued)
Parameter Test condition Min Typ Max Unit
70 2
100 2.5
130
k V RMS dB
SIN Gin_min
Input separation Minimum input gain
80 -1 29 1.5
100 0 30 2 1 31 2.5
dB dB dB
Gin_max Maximum input gain Gstep Step resolution
Volume control Ri Crange Av_max Astep EA Volume control input resistance Volume control range Max. attenuation Step resolution Attenuation set error AV = 0 to -24 dB AV = -24 to -47 dB Tracking error AV = 0 to -24 dB AV = -24 to -47 dB VDC Amute DC step Mute attenuation
(1)
20 45 45 0.5 -1.0 -1.5
33 47 47 1 0 0 0 0 0 0.5
50 49 49 1.5 1.0 1.5 1 2 3
k dB dB dB dB dB dB dB mV mV dB
E
adjacent attenuation steps from 0 dB to Av_max 80
100
Bass control Gb Bstep RB
Control range Step resolution Internal feedback resistance
(1)
Max. boost/cut
12.0 14.0 16.0 1 33 2 44 3 55
dB dB k
Treble control Gt Tstep
Control range Step resolution
(1)
Max. boost/cut
13.0 14.0 15.0 1 2 3
dB dB
Mid-range control Gm Mstep RM
Control range Step resolution Internal feedback resistance
Max. boost/cut
12.0 14.0 16.0 1 18.75 2 25 3 31.25
dB dB k
5/23
Electrical specifications Table 5.
Symbol
TDA7439
Electrical characteristics (continued)
Parameter Test condition Min Typ Max Unit
Speaker attenuators Crange Sstep
E
Control range Step resolution Attenuation set error DC step Mute attenuation AV = 0 to -20 dB AV = -20 to -56 dB
70 0.5 -1.5 -2
76 1 0 0 0
82 1.5 1.5 2 3
dB dB dB dB mV dB
A
VDC Amute
Adjacent attenuation steps 80
100
Audio outputs VCLIP RL RO Clipping level Output load resistance Output impedance d = 0.3% 2.1 2 10 3.5 40 3.8 70 4.1 2.6 Vrms k V
VOUTDC DC voltage level General ENO Et S/N SC d Output noise All gains = 0 dB; BW = 20 Hz to 20 kHz flat AV = 0 to -24 dB AV = -24 to -47 dB Signal to noise ratio Channel separation, left/right Distortion AV = 0, VI = 1 V RMS All gains 0 dB, VO = 1 V RMS
5 0 0 95 80 106 100 0.01
15 1 2
V dB dB dB dB
Total tracking error
0.08
%
Bus input VIL VIH IIN VO Input low voltage Input high voltage Input current Output voltage SDA acknowledge VIN = 0.4 V IO = 1.6 mA 3 -5 0 0.4 5 0.8 1 V V A V
1. For bass, mid-range and treble response: the center frequency and the response quality can be set by the external circuitry.
6/23
TDA7439 Figure 3. Test circuit
5.6nF 2.2F 2.7K 18nF MIN(L) 5.6K 22nF 100nF 100nF
Electrical specifications
MUXOUTL L-IN1 0.47F L-IN2 0.47F L-IN3 0.47F L-IN4 0.47F 14 100K 0/30dB 2dB STEP 100K 9 100K 8 100K 7 100K INPUT MULTIPLEXER + GAIN 13 100K 12 100K G 11 100K
INL 15
TREBLE(L) 16 27
MOUT(L) 26 RM 25
BIN(L) 23 RB
BOUT(L) 24
VOLUME
TREBLE
MIDDLE
BASS
SPKR ATT LEFT
6
LOUT
30 I CBUS DECODER + LATCHES
2
R-IN1 0.47F R-IN2 0.47F R-IN3 0.47F R-IN4 0.47F
10
1 29
SCL SDA DIGGND
G
VOLUME
TREBLE
MIDDLE
BASS
SPKR ATT RIGHT VREF
5
ROUT
3 RM 17 MUXOUTR INR 18 TREBLE(R) 28 MIN(R) 19 20 21 BIN(R) RB 22 BOUT(R) SUPPLY 4
VS AGND
2 CREF
MOUT(R)
2.2F 5.6nF
18nF 2.7K
22nF 100nF 5.6K
100nF
10F
D95AU339B
7/23
Application suggestions
TDA7439
3
Application suggestions
The first and the last stages are volume control blocks. The control range is 0 to -47 dB and mute for the first stage and 0 to -79 dB and mute for the last one. Both control blocks have a step resolution of 1 dB. This very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7439 audio processor provides 3 bands of tone control (bass, mid-range and treble).
3.1
3.1.1
Tone control
Bass, mid-range stages
The bass and the mid-range cells have the same structure. However, the bass cell has an internal resistor RB of typically 44 k whilst the mid-range cell has an internal resistor RM of typically 25 k. Several filter types can be implemented by connecting external components to the bass/mid IN and OUT pins. Typical responses are shown in Figure 8, Figure 9 and Figure 11. Figure 4. Bass/mid-range filter implementation
Ri internal IN C1 R2
D95AU313
OUT C2
Figure 4. refers to the basic T-type band-pass filter. Starting from the filter component values (R1 (internal) and R2, C1, C2 (external)) then the centre frequency fC, the gain Av at maximum boost and the filter Q factor are computed as follows:
1 f C = ---------------------------------------------------------------2 R1 R2 C1 C2 A V = R2C2 + R2C1 + RiC1 ----------------------------------------------------------R2C1 + R2C2 R1 R2 C1 C2 Q = ------------------------------------------------R2C1 + R2C2
8/23
TDA7439
Application suggestions Transposing and solving for the external component values we get:
AV - 1 C1 = ----------------------------------------2 Fc Ri Q Q C1 C2 = ----------------------------2 AV - 1 - Q AV - 1 - Q R2 = --------------------------------------------------------------------2 C1 Fc ( A V - 1 ) Q
2 2
3.1.2
Treble stage
The treble stage is a high-pass filter whose time constant is fixed by an internal resistor (25 k typically) and an external capacitor connected between treble pins and ground. Typical responses are shown in Figure 10 and Figure 11.
3.2
Pin CREF
The suggested value of 10 F for the reference capacitor (CREF), connected to pin CREF, can be reduced to 4.7 F if the application requires faster power-on.
3.3
Electrical characteristics
Figure 5. THD vs frequency Figure 6. THD vs RLOAD
9/23
Application suggestions
TDA7439
Figure 7.
Channel separation vs frequency
Figure 8.
Bass filter response
Figure 9.
Mid-range filter response
Figure 10. Treble filter response
Figure 11. Typical tone response
10/23
TDA7439
I2C bus interface
4
I2C bus interface
Data transmission from the microprocessor to the TDA7439 and vice versa takes place through the 2-wire I2C bus interface. This consists of the data and clock lines, SDA and SCL. Pull-up resistors to the positive supply voltage must be used (there are no internal pull-ups).
4.1
Data validity
The data on the SDA line must be stable during the high period of the clock as shown in Figure 12. SDA is allowed to change only when SCL is low.
4.2
Start and stop conditions
As shown in Figure 13 a start condition is a high to low transition of SDA while SCL is high. The stop condition is a low to high transition of SDA while SCL is high.
4.3
Byte format
Every byte transferred on the SDA line must contain 8 bits. The MSB is transferred first. There is also provision for an acknowledge bit to follow each byte to indicate that the data has been received.
4.4
Acknowledge
The master (P) puts a resistive high level on SDA during the acknowledge clock pulse (see Figure 14). The peripheral (audio processor) that acknowledges has to pull down (low) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the high level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.
4.5
Transmission without acknowledge
Suppressing the audio processor acknowledge detection enables the P to use a simpler transmission: it simply waits for one clock, without checking the slave acknowledging, and then sends the new data. This approach has, of course, less protection from transmission errors.
11/23
I2C bus interface Figure 12. Timing diagram of the data on the I2C bus
SCL
TDA7439
SDA Data stable Data can change when clock high when clock low
Figure 13. Timing diagram of the start/stop
SCL
SDA Start Stop
Figure 14. Timing diagram of the acknowledge
SCL
1
2
6
7
8
9
SDA Start
MSB Acknowledge from receiver
4.6
Interface protocol
The interface protocol comprises:
" " " " "
a start condition (S) a chip-address byte, containing the TDA7439 address a sub-address byte including an auto address-increment bit a sequence of data bytes (N bytes + acknowledge) a stop condition (P).
Figure 15. SDA addressing and data
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X B DATA SUBADDRESS LSB ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU420
S = Start, ACK = Acknowledge, B = Auto increment, P = Stop
12/23
TDA7439
I2C bus transmission examples
5
5.1
I2C bus transmission examples
No address incrementing
The TDA7439 receives a start condition followed by the correct chip address, then a sub address with the bit B = 0 (for no address increment), then the data bytes to be sent to the sub address and finally a stop condition. Figure 16. SDA addressing and data for B = 0
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 0 D3 D2 D1 D0 ACK MSB DATA DATA LSB ACK P
D96AU421
5.2
Address incrementing
The TDA7439 receives a start condition followed by the correct chip address, then a sub address with the B = 1 for address incrementing; now it is in a loop condition with an automatic increase of the sub address up to D[3:0] = 0x7. That is, the data for sub addresses from D[3:0] = 1000 (binary) to 1111 are ignored. In Figure 17 below, DATA1 is directed to the sub address sent (that is, D[3:0]), DATA2 is directed to the sub address incremented by 1 (that is, 1 + D[3:0]) and so forth until a stop condition is received to terminate the transmission. Figure 17. SDA addressing and data for B = 1
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 1 D3 D2 D1 D0 ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU422
Table 6.
Power-on-reset conditions
Parameter POR value IN2 28 dB MUTE 0 dB 2 dB 2 dB MUTE
Input selection Input gain Volume Bass Mid-range Treble Speaker
13/23
I2C bus addresses and data
TDA7439
6
6.1
I2C bus addresses and data
Chip address byte
The TDA7439 chip address is 0x88.
6.2
Sub-address byte
The function is selected by the 4-bit sub address as given in Table 7. The three MSBs are not used and bit D4 selects address incrementing (B = 1) or single data byte (B = 0). Table 7.
MSB D7 X X X X X X X X D6 X X X X X X X X D5 X X X X X X X X D4 B B B B B B B B D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1
Function selection: sub-address byte
LSB Function D0 0 1 0 1 0 1 0 1 Input selector Input gain Volume Bass gain Mid-range gain Treble gain Speaker attenuation, R Speaker attenuation, L
6.3
Data bytes
The function value is changed by the data byte as given in the following tables, Table 8 to Table 14. In the tables of input gain, volume and attenuation, not all values are shown. A desired intermediate value is obtained by setting the three LSBs to the appropriate value. Table 8.
MSB D7 X X X X D6 X X X X D5 X X X X D4 X X X X D3 X X X X D2 X X X X D1 0 0 1 1
Input selector value (sub address 0x0)
LSB Input multiplexer D0 0 1 0 1 IN4 IN3 IN2 IN1
14/23
TDA7439 Table 9.
MSB D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 X X X X X X X X X X X X X X X X D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
I2C bus addresses and data Input gain value (sub address 0x1)
LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input gain 2-dB steps 0 dB 2 dB 4 dB 6 dB 8 dB 10 dB 12 dB 14 dB 16 dB 18 dB 20 dB 22 dB 24 dB 26 dB 28 dB 30 dB
Table 10.
MSB D7 X X X X X X X X X X X X X X D6 0 0 0 0 0 0 0 0 0 0 0 0 0 X
Volume value (sub address 0x2)
LSB D5 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D4 0 0 0 0 0 0 0 0 0 1 1 0 0 1 D3 0 0 0 0 0 0 0 0 1 0 1 0 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 X D1 0 0 1 1 0 0 1 1 0 0 0 0 0 X D0 0 1 0 1 0 1 0 1 0 0 0 0 0 X Volume 1-dB steps 0 dB -1 dB -2 dB -3 dB -4 dB -5 dB -6 dB -7 dB -8 dB -16 dB -24 dB -32 dB -40 dB MUTE
15/23
I2C bus addresses and data Table 11.
MSB D7 X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X D4 X X X X X X X X X X X X X X X D3 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0
TDA7439
Bass gain value (sub address 0x3)
LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Bass gain 2-dB steps -14 dB -12 dB -10 dB -8 dB -6 dB -4 dB -2 dB 0 dB 2 dB 4 dB 6 dB 8 dB 10 dB 12 dB 14 dB
Table 12.
MSB D7 X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X
Mid-range gain value (sub address 0x4)
LSB D5 X X X X X X X X X X X X X X X D4 X X X X X X X X X X X X X X X D3 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Mid-range gain 2-dB steps -14 dB -12 dB -10 dB -8 dB -6 dB -4 dB -2 dB 0 dB 2 dB 4 dB 6 dB 8 dB 10 dB 12 dB 14 dB
16/23
TDA7439 Table 13.
MSB D7 X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X D4 X X X X X X X X X X X X X X X D3 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0
I2C bus addresses and data Treble gain value (sub address 0x5)
LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Treble gain 2-dB steps -14 dB -12 dB -10 dB -8 dB -6 dB -4 dB -2d B 0 dB 2 dB 4 dB 6 dB 8 dB 10 dB 12 dB 14 dB
Table 14.
MSB D7 X X X X X X X X X X X X X X X D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Speaker attenuation value (sub address 0x6, 0x7)
LSB D5 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 D4 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 D3 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 D1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 D0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 Speaker attenuation 1-dB steps 0 dB 1 dB 2 dB 3 dB 4 dB 5 dB 6 dB 7 dB 8 dB 16 dB 24 dB 32 dB 40 dB 48 dB 56 dB
17/23
I2C bus addresses and data Table 14.
MSB D7 X X X D6 1 1 1 D5 0 0 1 D4 0 0 1 D3 0 1 1 D2 0 0 X D1 0 0 X
TDA7439
Speaker attenuation value (sub address 0x6, 0x7) (continued)
LSB D0 0 0 X Speaker attenuation 1-dB steps 64 dB 72 dB MUTE
18/23
TDA7439
Chip input/output circuits
7
Chip input/output circuits
Figure 18. Pin 2 Figure 19. Pins 5, 6
VS
VS
VS 20K
ROUT LOUT 24
CREF 20K
20A
D96AU430
D96AU434
Figure 20. Pins 7, 8, 9, 10, 11, 12, 13, 14 Figure 21. Pins 15, 17
VS VS 20A MIXOUT
VS 20A
IN
100K
GND
VREF
D96AU425
D96AU426
Figure 22. Pins 20, 25
VS 20A
Figure 23. Pins 19, 26
VS 20A
25K MOUT(L) MOUT(R)
D96AU431
25K MIN(L) MIN(R)
D96AU431
19/23
Chip input/output circuits
TDA7439
Figure 24. Pins 21, 23
VS 20A
Figure 25. Pins 22, 24
VS 20A
44K 44K BIN(L) BIN(R)
D96AU428
BOUT(L) BOUT(R)
D96AU429
Figure 26. Pins 27, 28
VS 20A TREBLE(L) TREBLE(R) 50K
Figure 27. Pin 30
20A SCL
D96AU433
D96AU424
Figure 28. Pin 1
Figure 29. Pins 16, 18
VS 20A 20A
SDA
INL INR 33K
D96AU423 D96AU427
VREF
20/23
TDA7439
Package information
8
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
mm MIN. A A1 A2 B B1 C D E E1 e e1 L M S 0.31 2.54 0.51 3.05 0.36 0.76 0.20 27.43 10.16 8.38 3.81 0.46 0.99 0.25 27.94 10.41 8.64 1.778 10.16 3.30 3.81 0.10 4.57 0.56 1.40 0.36 28.45 11.05 9.40 TYP. MAX. 5.08 0.020 0.12 0.014 0.030 0.008 1.08 0.400 0.330 0.15 0.018 0.039 0.01 1.10 0.410 0.340 0.070 0.400 0.13 0.15 0.18 0.022 0.055 0.014 1.12 0.435 0.370 MIN. inch TYP. MAX. 0.20
DIM.
OUTLINE AND Outline and mechanical data MECHANICAL DATA
0(min.), 15(max.) 0.012
SDIP30 (0.400 in.) SDIP30 (0.400")
21/23
Revision history
TDA7439
9
Revision history
Table 15.
Date Jan-2004 Jun-2004 21-Mar-2008
Document revision history
Revision 9 10 11 Changes Initial release in EDOCS DMS Modified presentation Updated titles to Figure 9 and Figure 10 Minor updates to presentation
22/23
TDA7439
Please Read Carefully:
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